The present invention generally relates to a semi-conductor decoder circuit and more particularly, to a decoder circuit for a memory circuit constructed with CMOS (complementary metal oxide semi-conductor) transistors.
Following the recent rapid progress in processing techniques, there has been a marked increase in the memory capacity of a semi-conductor memory, while memory cell size has tended to decrease in inverse proportion to the memory capacity owing to the restriction in the chip size.
Generally, in an asynchronous CMOS memory, the decoder section is constituted by NAND circuits as shown in FIG. 1, and for the NAND circuits of this kind, there are employed circuits constructed of NMOS (n-channel metal oxide semi-conductor) transistors connected to each other so as to be vertically arranged. However, the NAND circuit construction as described above has such a disadvantage that its ON resistance is undesirably increased, with a consequent prolonged discharge time. Moreover, following the reduction of the memory cell size owing to the reason described earlier, the gate width of the NMOS transistor becomes still smaller in an ordinary layout system, and therefore, the inconvenience that the discharge time is prolonged still further, can not be avoided.
More specifically, in the decoder section of the asynchronous CMOS memory as illustrated in FIG. 1, although there are provided the NAND circuits respectively applied with N inputs of A'.sub.1 to A'.sub.N, these N input NAND circuits NAND .sub.1, NAND.sub.2, . . . and NAND.sub.K present an obstacle for high speed operation, and therefore, various proposals have been made up to the present time to modify circuit construction and layout systems in order to eliminate the disadvantage as described above.
In FIG. 2, there is shown the simplest construction of a CMOS N input NAND circuit conventionally employed, in which N number of PMOS (p-channel metal oxide semi-conductor) transistors PT are connected in parallel to each other, while N number of NMOS transistors NT are connected to be vertically arranged in series with each other between a common junction j of said PMOS transistors PT and the ground, with input signals A'.sub.i /A'.sub.i (i=1 through N) being applied to respective gates of said PMOS transistors PT and NMOS transistors NT so as to function as the NAND circuit.
In FIG. 3, showing a layout pattern of an arrangement of the above NAND circuits, for example, NAND.sub.1 and NAND.sub.2, regions surrounded by solid lines are diffusion areas 1 and 2, and 2N pieces of signal lines A'.sub.1, A'.sub.1 ... A'N, A'N are formed by Al wiring, while polysilicon layers 3 (shown by hatched lines) are further formed on gate insulating films forming the NMOS transistors NT so as to overlap the Al wiring. In FIG. 3, marks .circle. represent contact holes for establishing connections between the Al wiring and the polysilicon layers 3 of the NMOS transistor gate electrodes, and marks x show connections between the Al wiring and the diffusion areas 1 and 2. In the circuit arrangement of FIG. 3, N pieces of NMOS transistors NT are employed per one NAND circuit, and the gate width of each transistor must be accommodated within a memory cell length LMC. On the assumption that the gate width of the NMOS transistor equivalent to the memory cell length LMC is denoted by W.sub.M, the substantial gate width W.sub.1 for the NMOS portion which must be vertically arranged is represented by an equation, ##EQU1##
Subsequently, FIG. 4 shows an improved circuit of the conventional circuit of FIG. 2, while FIG. 5 represents a layout pattern thereof. In FIG. 4, (N+1)/2 pieces of NMOS transistors NT are employed for one NAND circuit, and the gate widths of the transistors having A'.sub.2 /A'.sub.2 to A'.sub.N /A'.sub.N as the inputs can be expanded to a value equivalent to 2LMC. Although the MOS transistor having the gate width larger than that in the conventional circuit of FIG. 2 may be obtained by the above arrangement, the substantial gate width W.sub.2 in this case is merely one represented by an equation, ##EQU2## and it can not be said that a fully satisfactory improvement has been achieved, even with respect to the circuits vertically arranged in multi-stages, and thus, a sufficiently high speed operation has not been achieved as yet by any of the conventional systems due to the hindrance resulting from the vertically staged connection of NMOS transistors.